1. Field of the Invention
The present invention relates to a multiprocessor system in which a plurality of processors are connected to a shared memory through an address bus and a data bus.
2. Description of the Prior Art
A multiprocessor using a shared memory composed of only a single bank in memory access is known heretofore as described in "Report on Computer System Research", CPSY90-4, The Institute of Electronics, Information and Communication Engineers of Japan, Apr. 20, 1990, pp. 25-32, (hereinafter referred to as "first reference").
The first reference has proposed a split bus in which a system bus is once released after a sender unit such as a processor transmits an order (address/ data) and a receiver unit acquires the ownership of the system bus to answer the sender unit when it has becomes ready for answering.
Further, the first reference has proposed provision of a system bus interface control circuit (communication buffer) for storing a plurality of orders or answers under the consideration that such a plurality of orders may be given from a plurality of units such as processors, memories, input-output devices, and the like. For example, the system bus interface control circuit is provided in a bus input-output portion of a processor unit.
According to the proposed system, different data transfer such as address transfer from a unit C to a unit B can be executed in a time space between address transfer from a unit A to the unit B and data transfer from the unit B to the unit A.
As a result, the occupation of the shared system bus by one unit for a long time can be prevented, so that a high transfer throughput in this type of multiprocessor system can be expected.
On the other hand, a memory access pipeline system in which memory access can be made without the necessity of waiting for completion of the previous memory access is disclosed in "Computer Architecture", The OHMsha Ltd., Aug. 30, 1988, pp. 179-184, (hereinafter referred to as "second reference"). In the disclosed system, the memory is divided into a plurality of banks. Further, an access queue and a data queue are added to the memory in order to buffer access requests inputted successively and read data outputted successively.
According to the disclosed system, high-speed memory access can be attained because a succeeding request need not wait completion of a preceding request if these two access requests are addressed to different memory banks, respectively.
Further, the second reference discloses a hardware system for pipeline access to a memory divided into a plurality of banks. As the hardware system, proposed is a pipeline access system having a plurality of memory address resisters and a plurality of data latches corresponding to the plurality of banks.